Semiconductor devices are found in many products in the fields of entertainment, communications, networks, computers, and household markets. Semiconductor devices are also found in military, aviation, automotive, industrial controllers, and office equipment. The semiconductor devices perform a variety of electrical functions necessary for each of these applications.
The manufacture of semiconductor devices involves formation of a wafer having a plurality of die. Each semiconductor die contains hundreds or thousands of transistors and other active and passive devices performing a variety of electrical functions. For a given wafer, each die from the wafer typically performs the same electrical function. Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer. The finished wafer has an active side containing the transistors and other active and passive components. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation.
One goal of semiconductor manufacturing is to produce a package suitable for faster, reliable, smaller, and higher-density integrated circuits (IC) at lower cost. Flip chip packages or wafer level packages (WLP) are ideally suited for ICs demanding high speed, high density, and greater pin count. Flip chip style packaging involves mounting the active side of the die facedown toward a chip carrier substrate or printed circuit board (PCB). The electrical and mechanical interconnect between the active devices on the die and conduction tracks on the carrier substrate is achieved through a solder bump structure comprising a large number of conductive solder bumps or balls. The solder bumps are formed by a reflow process applied to solder material deposited on metal contact pads which are disposed on the semiconductor substrate. The solder bumps are then soldered to the carrier substrate. The flip chip semiconductor package provides a short electrical conduction path from the active devices on the die to the carrier substrate in order to reduce signal propagation, lower capacitance, and achieve overall better circuit performance.
FIG. 1 illustrates a portion of flip chip 10 with a solder bump 12 formed on metal contact pad 14. The solder bump 12 is then metallurgically and electrically connected to metal contact pad 15 on substrate 16 using a solder reflow process. To connect solder bump 12 and contact pad 15, a solder resist or mask opening 18 is disposed over a surface of the substrate to confine the solder reflow to the physical boundaries of contact pad 15, see FIG. 2a. Due to manufacturing alignment tolerances as to the relative position between contact pad 15 and solder resist opening 18, contact pad 15 is made substantially larger than solder resist opening 18 to ensure that the full metal area of the contact pad is exposed, given the alignment tolerance of the solder resist opening. In generally, the minimum size of contact pad 15 is Pmin=SRO+2*SRR, where SRO is the minimum solder resist opening required to ensure good metallurgical connection and SRR is the solder resist alignment tolerance, also known as solder registration. In one example, if solder resist opening 18 is 90 microns and the solder resist alignment tolerance is 25 microns, then, according to the known design rule, contact pad 15 is made 140 microns in diameter. Thus, under the known design rule, and given the maximum manufacturing alignment tolerance, the solder resist opening always falls within the contact pad and leaves no voids or empty space around the pad, as shown in FIG. 2b. 
Unfortunately, the larger contact pad required to ensure that the solder resist opening always falls within the full metal area of the contact pad limits the metal signal trace or track routing density that can be achieved on the substrate. The larger contact pad necessarily reduces trace routing density as fewer traces can be placed between the contact pads. In addition, the larger contact pad translates to fewer contacts pads per unit area of the substrate.